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Devil in the Details: Trends in ASIC Prototyping
By John Blyler Chips continue to grow in complexity. This is nothing new. But even at the existing process nodes of 180nm and 130nm, complexity is increasing as designers attempt to squeeze in more...
View ArticleCOTS Issues
Click here to view the embedded video. What can go wrong when you use commercial off-the-shelf parts in military applications? We asked Daren McClearnon, an ESL specialst at Agilent.
View ArticleThe Week in Review: March 13
If you think things are bad, be glad you’re not in the Taiwanese foundry business—where the pain level is strangely uniform. TSMC’s sales dropped 59.5% in February compared to the same month last...
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What Are They Designing?
By John Blyler A just completed EDA tools and technology survey of 140 engineers conducted over the past several weeks shows a strong push into full-custom devices and FPGAs. In fact, 32% of the ICs...
View ArticleFPGAs Gain Ground In China
By The EEFocus Staff FPGAs are booming in China. When Clement Cheung, director of marketing and applications at Xilinx Asia Pacific showed up to give a speech recently, he was worried not many people...
View ArticleIntegrated IP Goes Vertical
By Ed Sperling The consolidation of intellectual property from small developers to large players with integrated IP blocks is accelerating. Large IP companies are now developing integrated suites that...
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System Bits: April 24
Cut, clarity, computer? Diamonds are forever…or, at least, the effects of one particular diamond on quantum computing may be, according to a team that includes scientists from USC that built a quantum...
View ArticleFPGA Design And Verification in Mechatronic Applications
The biggest challenge in using FPGA devices may be one of methodology. FPGA designers are familiar with HDL-based requirements-driven design methodologies for digital electronics. But how can...
View ArticleWhat Are They Designing?
By John Blyler A just completed EDA tools and technology survey of 140 engineers conducted over the past several weeks shows a strong push into full-custom devices and FPGAs. In fact, 32% of the ICs...
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Fundamental Laws of (FPGA) Nature: Similar, Yet Different
Chris A. Ciufo, Senior Editor Lattice and Xilinx muse on parallelism, partial reconfigurability, and the state-of-the-art in IP and EDA tools. Most hardware and software designers end up dealing with...
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Does Altera Have “Big Data” Communications on the Brain?
By Chris A. Ciufo, Editor-in-Chief In wireless, wireline and financial big-data applications, moving all those packets needs prodigious FPGA resources, not all of which Altera had before its recent...
View ArticleBlog Review October 10 2013
By Caroline Hayes At the TSMC Open Innovation Platform (TSMC OIP) Ecosystem Forum, Richard Goering hears that 16mm FinFET design and 3D ICs are moving closer to volume production. Dr Cliff Hou, vice...
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Connected IP Blocks: Busses or Networks?
Gabe Moretti David Shippy of Altera, Lawrence Loh from Jasper Design, Mentor’s Steve Bailey, and Drew Wingard from Sonics got together to discuss the issues inherent in connecting IP blocks whether in...
View ArticleWhat Are They Designing?
By John Blyler A just completed EDA tools and technology survey of 140 engineers conducted over the past several weeks shows a strong push into full-custom devices and FPGAs. In fact, 32% of the ICs...
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Fundamental Laws of (FPGA) Nature: Similar, Yet Different
Chris A. Ciufo, Senior Editor Lattice and Xilinx muse on parallelism, partial reconfigurability, and the state-of-the-art in IP and EDA tools. Most hardware and software designers end up dealing with...
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Does Altera Have “Big Data” Communications on the Brain?
By Chris A. Ciufo, Editor-in-Chief In wireless, wireline and financial big-data applications, moving all those packets needs prodigious FPGA resources, not all of which Altera had before its recent...
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Week in Review October 29
Altera chooses quad-core 64bit ARM Cortex-A53 for Stratix 10 SoCs At ARM TechCon, this week, Altera announced that its Stratix 10 SoC devices, manufactured on Intel’s 14nm Tri-Gate process, will...
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Next Year in EDA: What Will Shape 2015
Gabe Moretti, Senior Editor The Big Picture Having talked to Cadence, Mentor and Synopsys I think it is very important to hear what the rest of the EDA industry has to say about the coming year. After...
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ASIC Prototyping With FPGA
Zibi Zalewski, General Manger of the Hardware Products Division, Aldec When I began my career as a verification products manager, ASIC/SoC verification was less integrated and the separation among...
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